收藏本站
W972GG6JB
7.3.10 No-Operation Command
( CS = "L", RAS = "H", CAS = "H", WE = "H", CKE, BA0, BA1, BA2, A0 to A13 = Don?t Care )
The No-Operation command simply performs no operation (same command as Device Deselect).
7.3.11 Device Deselect Command
( CS = "H", RAS , CAS , WE , CKE, BA0, BA1, BA2, A0 to A13 = Don?t Care )
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
7.4
Read and Write access modes
The 16 Mbit x 16 I/O x 8 Bank chip has a page length of 1024 bits (defined by CA0 to CA9) . The page
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will
initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is
strictly restricted to specific segments of the page length.
*
length of 1024 is divided into 256 or 128 uniquely addressable boundary segments depending on
burst length, 256 for 4 bit burst, 128 for 8 bit burst respectively. A 4-bit or 8-bit burst operation will
occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the
device during the Read or Write Command (CA0 to CA9). The second, third and fourth access will
also occur within this group segment. However, the burst order is a function of the starting address,
and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting.
However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one
reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary
respectively. The minimum CAS to CAS delay is defined by t CCD , and is a minimum of 2 clocks for
read or write cycles.
Note: Page length is a function of I/O organization and column addressing
16M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits
7.4.1
Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write
command to be issued immediately after the RAS bank activate command (or any time during the
RAS - CAS -delay time, t RCD , period). The command is held for the time of the Additive Latency (AL)
before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the
CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the t RCDmin ,
then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined
as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS
Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts. (Example timing
waveforms refer to 10.10 and 10.11 seamless burst read/write operation diagram in Chapter 10)
7.4.1.1
Examples of posted CAS operation
Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown
in Figures 14 and 15, respectively.
Publication Release Date: Nov. 29, 2011
- 23 -
Revision A02
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
W9751G6IB-25 IC DDR2-800 SDRAM 512MB 84-WBGA
W9751G6KB-25 IC DDR2 SDRAM 512MBIT 84WBGA
W9812G6JH-6I IC SDRAM 128MBIT 54TSOPII
W9816G6IH-6I IC SDRAM 16MBIT 50TSOPII
W9825G6JH-6I IC SDRAM 256MBIT 54TSOPII
W9864G6JH-6I IC SDRAM 64MBIT 54TSOPII
WM-5614 CABINET WALL MOUNT 37.25X17.9"
WRR-2244 RACK WALL MOUNT RELAY 42" X 19"
相关代理商/技术参数
W972GG8JB 制造商:WINBOND 制造商全称:Winbond 功能描述:32M ??′ 8 BANKS ??′ 8 BIT DDR2 SDRAM
W972GG8JB-18 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 1.875NS BGA
W972GG8JB-25 制造商:Winbond Electronics Corp 功能描述:2GMB DDRII 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 60WBGA
W972GG8JB-25I 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA
W972GG8JB-3 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS
W9751G6IB-25 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR)
W9751G6JB 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9751G6JB-25 制造商:Winbond Electronics Corp 功能描述:512GB DDRII